A programmable switch normally has a memory connected to the gate of a pass transistor functioning as a switch, and controls switching on and off of the pass transistor in accordance with data that is stored in the memory. A typical FPGA (Field Programmable Gate Array) is formed with logic elements and a programmable switch array. Each of the programmable switches serves to selectively connect the logic elements.
According to a known method, a nonvolatile programmable switch is formed with two nonvolatile memory transistors and a pass transistor. According to this method, the nonvolatile memory transistors can be of a floating gate type, for example. A supply voltage (Vdd) or grand voltage (0 V) is input to the gate of the pass transistor via one of the two nonvolatile memory transistors. In a case where writing in the nonvolatile memory transistors is performed by a FN (Fowler-Nordheim) tunneling current write method (hereinafter also referred to as the FN method), the respective gates of the two nonvolatile memory transistors need to be connected to different word lines. This is because different gate voltages have to be applied to the two nonvolatile memory transistors in order to realize selective writing (one of the two nonvolatile memory transistors is selectively written).
According to another known method, a programmable logic switch is formed with two nonvolatile memory transistors, a pass transistor, and an access transistor. The nonvolatile memory transistors can be of a floating gate type, for example. Vdd or 0 V is input to the gate of the pass transistor via one of the two nonvolatile memory transistors. According to this method, the gates of the two nonvolatile memory transistors are connected to the same word line, and selective writing is performed by a channel hot electron write method (hereinafter also referred to as the CHE method).
The limit size of a writable memory transistor according to the FN method is normally smaller than the limit size of a writable memory transistor according to the CHE method. According to the CHE method, high-energy electrons (hot electrons) generated due to a potential difference between the source and the drain are injected into the charge storage film by a voltage applied to the gate. Normally, in a region where the gate length of the transistor is 100 nm or shorter, the hot electron injection efficiency becomes smaller as the gate length becomes shorter.
The cell area of a programmable switch is smaller where the number of word lines per cell is smaller and the memory transistor size is smaller. With smaller cell areas, a larger number of circuit components can be mounted on a chip with the same area, and a high-performance FPGA can be realized. Alternatively, the same number of circuit components can be mounted on a chip with a smaller area, and the cost per chip can be lowered.
Therefore, to realize a nonvolatile programmable switch having a smaller area, there is a demand for a cell structure in which the FN method is applicable and the number of word lines per cell is one. At present, however, there is not a known method for realizing such a cell structure.